The product is discontinued. For any queries, please contact, support@slscorp.com.

ONFI Controller IP Core is the intermediate stage between NAND Flash memory and master controller. It is designed to have high speed solution to manage Raw NAND Flash application. It supports Open NAND Flash Interface Working Group (ONFI) 2.2 standard. Two advanced architectures - register based and descriptor based provides high speed performance, flexibility, data integrity and device compatibility. Descriptor based architecture reduces amount of CPU intervention.

The ONFI Controller IP Core gives full support for Altera’s SOPC Builder and Qsys based systems and provides communication between processor and NAND Flash device using Avalon interface.

Snap On Board:

SLS has developed ONFI 2.0 HSMC snap on board that can be used with any host board with HSMC interface. Contact info@slscorp.com for details.

Block Diagram:

Features:

• Supports ONFI 2.3 standard command set
• Supports integrated 32 bit DMA interface selection
• Buffer with configurable buffer depth for read and write operation
• Supports up to 4 NAND Flash device selection
• Supports 4KB and 8KB page size
• Supports 8 bit data bus
• Supports 4, 8 and 12 bit Error Correction per 512 bytes
• Supports command repeat and auto address increment functionality
• Supports Multiplane (interleave) and Multi LUN operation
• Supports interrupt driven functionality
• Avalon Bus Compliant

Implementation Results on Cyclone IV E:

Implementation Results of ECC on Cyclone IV E:

Verification:

• The IP Core is tested on
  • SLS USB 3.0 Development Board
  • Altera Cyclone III Development Board (3C120)
  • Altera Cyclone III Starter Kit
  • Altera Stratix IV GX Development Board
• ONFI Controller IP core's functionality is verified in Altera ModelSim simulation software.

Deliverables:

Downloads:

• ONFI Controller Documents