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USB 2.0 Host Controller

Model No. IPRUSB2SFP004

Rating: 5/5




The USB 2.0 Host Controller IP Core is a 32-bit Avalon/AXI/AHB interface compliant core and supports ULPI interface. It supports High Speed (HS), Full Speed (FS) and Low Speed (LS) modes.

IP core has been implemented in Verilog HDL and its functionality has been verified using different test cases in simulation environment as well as on hardware. It is provided as ready to use component and hence can be easily integrated in system.

Block Diagram:



  • Supports Low Speed (1.5 Mbps), Full Speed (12 Mbps) and High Speed (480 Mbps) modes
  • Supports Control, Bulk and Interrupt transfers
  • Contains two different interface for Control Port and Data Port to improve Clock Domain Crossing (CDC) performance
  • Supports Asynchronous Avalon/AXI/AHB clock interface
    • Enables you to run CPU interface at clock frequency independent of ULPI bus
  • Supports SPLIT transfer
  • Optimized TD (Transfer Descriptor) structure
  • Configurable memory depth
    • Enables you to reduce resource utilization depending on application needs
  • Supports UTMI + Low Pin interface (ULPI) interface
  • Meets Design Assistant guidelines
  • Mass storage class speed performance
    • Upto 14 MBPS speed for read operation
    • Upto 11 MBPS speed for write operation

FPGA Supported:

FPGASupported Device Family
Intel Cyclone 10, Cyclone V, Cyclone IV, Cyclone III
Arria 10, Arria V, Arria II
Stratix 10, Stratix V, Stratix IV, Stratix III
Max 10
Microchip PolarFire, PolarFire SoC
Xilinx Kintex, Vertex, Artix
Lattice Crosslink NX, Certus Pro NX



  • IP Core has been tested by interfacing it with USB 2.0 PHY (RN1133) on SLS HSIC development board.
  • It has also been verified under simulation environment.


ContentsEvaluation LicenseFull Development License
License Type One (1) month evaluation license at no cost
Note: License can be extended for another month after examining request (Evaluation Now)
Encrypted IP Core Perpetual license for development
Note: Other licensing schemes and source code are also available
Reference Design Included for respective Development board Included for respective Development board
Demonstration Mass Storage, Device Enumeration Mass Storage, Device Enumeration
HAL Drivers Included in Object Code Included in Object code
Note: Source Code available separately on request
Sample Applications (with C code) Mass Storage, Device Enumeration Mass Storage, Device Enumeration
Simulation Library Available Available
Technical Documents
  • IP Core User Guide
  • Hardware and Simulation Tutorial
  • HAL API User Guide
  • IP Core User Guide
  • Hardware and Simulation Tutorial
  • HAL API User Guide
Technical Support Pre sales support from support team 1 Year integration support



  • Set-up Box
  • Printer
  • Television
  • Music system
  • Mass storage


  • IP integration support available with the purchase of full version
  • Additional support on chargeable basis for a period of 3 months or more
  • IP Core modification support available at additional cost


  • OpenCore Plus Evaluation : 1 month evaluation license at no cost
  • Full : 1 Year development license with full version purchase for single project and single site
  • Renewal : OpenCore Plus Evaluation license update at discounted price




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    System Level Solutions Inc. 511 N. Washington Avenue,Marshall, Texas 75670. Ph: 001-408-852-0067