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I2C Master

Model No. IPRI2CMMFP001

Rating: Not Rated Yet



Avalon compliant I²C Master IP core provides an interface between Nios II processor and an I²C Slave device. It can work as a master transmitter or master receiver depending on working mode determined by Nios II processor. The I²C Master IP core incorporates all features required by the latest I²C specification including clock synchronization, arbitration, multi-master systems and fast-speed transmission mode.

The I²C Master IP core is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.

Block Diagram:


  • Compatible with Philips I²C standard
  • Two transmission speeds are supported; Normal: 100Kbps Fast: 400Kbps
  • Multi Master Operation
  • Software programmable clock frequency
  • Clock stretching and wait state generation
  • Software programmable acknowledge bit
  • Interrupt or bit-polling driven byte-by-byte data-transfers
  • Arbitration lost interrupt, with automatic transfer cancellation
  • Start/Stop/Repeated Start/Acknowledge generation
  • Start/Stop/Repeated Start detection
  • Bus busy detection
  • Supports 7 and 10bit addressing mode
  • Operates from a wide range of input clock frequencies

Implementation Results:

Supported FamilyResource UtilizationPerformance ( Avalon Clock - fmax )
Cyclone III228 LE170MHz
Cyclone IV227 LE120MHz
Cyclone V108 ALM235MHz
Stratix III115 ALUT200MHz
Stratix IV112 ALUT275MHz
Stratix V106 ALM325MHz
Arria II120 ALUT150MHz
Arria V108 ALM320MHz
MAX 10227 LE170MHz


  • I²C Master Core's functionality is verified in modelsim simulation software using test bench written in Verilog HDL
  • I²C Master IP is also tested by interfacing with RTC (Real Time Clock) and I²C EPROM on SLS UP3 Board


ContentsEvaluation LicenseFull Development License
License Type One (1) month evaluation license at no cost
Note: License can be extended for another month after examining request (Evaluation Now)
Encrypted IP Core Perpetual license for development
Note: Other licensing schemes and source code are also available
Reference Design Included for NEEK Kit (Cyclone III 3C25) Included for NEEK Kit (Cyclone III 3C25)
Nios II HAL Drivers Included in Source Code Included in Source Code
Nios II Sample Applications
  • I2C Controller application using Interrupt
  • RTC application using Interrupt
  • I2C Controller application using Interrupt
  • RTC application using Interrupt
Simulation Library Altera Modelsim Altera Modelsim
Technical Documents
  • IP Core User Guide
  • Hardware and Simulation Tutorial
  • HAL API User Guide
  • IP Core User Guide
  • Hardware and Simulation Tutorial
  • HAL API User Guide
Technical Support Pre sales support from support team 1 Year integration support for Altera Quartus II


  • Interface with microcontroller
  • Communication System





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System Level Solutions Inc. 511 N. Washington Avenue,Marshall, Texas 75670. Ph: 001-408-852-0067