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Easily build interconnection and expansion interfaces for your SoC design with industry standard IP Cores from SLS.

As a solution to System On a Programmable Chip, SLS provides following set of standard bus interfaces.

I²C Controller

Supported Devices:

MAX II, Cyclone, Cyclone II, Stratix, Stratix II, Stratix GX

Description:

  •  Avalon interconnect compliant
  •  Byte by byte data transfers is driven by interrupt or bit polling
  •  Arbitration-lost interrupt with automatic transfer cancellation
  •  Bus-busy detection
  •  Static synchronous design
  •  Implementation in verilog RTL

 

I²C Master

Supported Devices:

MAX II, Cyclone, Cyclone II, Stratix, Stratix II, Stratix GX

Description:

  •  Phillips IC specification version 1.0 compliant
  •  Clock synchronization, arbitration, multi-master systems and fast speed transmission mode
  •  Software programmable clock frequency and acknowledgment bit
  •  Static synchronous design

 

I²C Slave

Supported Devices:

MAX II, Cyclone, Cyclone II, Stratix, Stratix II, Stratix GX

Description:

  •  Compatible with Phillips IC Standard
  •  Supports Normal and Fast Speed
  •  7 Addressing modes support
  •  Static synchronous design

 

I²S Controller

Supported Devices:

MAX II, Cyclone, Cyclone II, Stratix, Stratix II, Stratix GX

Description:

  •  Phillips Inter IC Sound (IS) specification compliant
  •  Supports variable data width and sampling frequency between 4KHz to 96KHz
  •  Provides selection for Master/Slave mode

 

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