USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)
Model No. IPRUSB2SFP003
The USB 2.0 Device, Software Enumeration (USB20SR) IP Core is a RAM based USB 2.0 device core with 32-bit Avalon/AXI/AHB Lite interface and ULPI interface support. The core supports High Speed(480 Mbps) , Full Speed(12 Mbps) and Low Speed(1.5 Mbps) functionality.
IP core has been implemented in Verilog HDL and its functionality has been verified using different test cases in simulation environment as well as on hardware. It is provided as ready to use component and hence can be easily integrated in system
The package includes precompiled library of Host-BFM with predefined test cases for IP core simulation and verification.
Actual Performance Data
(For ULPI Ram based solution)
Benefits:
- Complete solution comprising of core, software and board for easy and quick implementation
- Reduced risk with proven, compliant technology
- Premier direct support from SLS IP designers
- Low system and license cost
- Software drivers included
Block Diagram:
Features:
- Supports LS (1.5 Mbps)*, FS (12 Mbps) and HS (480 Mbps) modes
- Supports Control, Bulk, Interrupt and Isochronous transfers
- Capable to support up to 31 endpoints (1 default control endpoint + 15 IN/OUT endpoints)
- Supports software configurable endpoints
- Supports Suspend, Resume and Remote Wakeup features
- Supports UTMI + Low Pin interface (ULPI) interface
- Supports Asynchronous Avalon/AXI/AHB Lite clock interface
- Preconfigured for 3 endpoints
- CONTROL
- IN
- OUT
- Configurable Memory depth
- Supports software controlled PHY register access
- Ready to use component
- Meets good design practices.
- Optimized resource count
*Low Speed (1.5 Mbps) support for different FPGAs is provided on special request,contact support@slscorp.com for more details.
FPGA Supported:
| FPGA | Supported Device Family |
|---|---|
| Intel | Cyclone V, Cyclone IV GX, Cyclone III Arria V, Arria II Stratix V, Stratix IV, Stratix III Max 10 |
| Microchip | PolarFire, PolarFire SoC |
| AMD | Ultrascale, Ultrascale+ |
| Lattice | Crosslink NX |
Verification:
- IP Core has been tested by interfacing it with USB 2.0 PHY on SLS CoreCommander development board.
- USB20SR IP core's functionality is verified in simulation software using test bench written in Verilog HDL.
Deliverables:
| Contents | Evaluation License | Full Development License |
|---|---|---|
| License Type | One (1) month evaluation license at no cost Note: License can be extended for another month after examining request (Evaluation Now) |
Encrypted IP Core Perpetual license for development Note: Other licensing schemes and source code are also available |
| Reference Design | Included for respective Development board | Included for respective Development board |
| Demonstration | Mass Storage, HID Mouse, Performance Test (Streaming Bulk IN and Bulk OUT) | Mass Storage, HID Mouse, Performance Test (Streaming Bulk IN and Bulk OUT) |
| HAL Drivers | Included in Object Code | Included in Object code Note: Source Code provided on request |
| Sample Applications (with C code) | Stream Read/Write | Stream Read/Write |
| Utilities | WinUSB based application | WinUSB based application |
| Technical Documents |
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| Technical Support | Pre sales support from support team | 1 Year integration support |
Downloads:
| << Back to USB 2.0 | Go to USB20HF >> |
* Contact support@slscorp.com for details on support
