This IP Core is no longer available for new designs as the TI’s USB 3.0 PHY (TI1310A) is discontinued. For any query, contact us.

USB 3.1 Gen 1 (USB 3.0) Embedded Host Controller IP Core is a 32-bit Avalon interface compliant core and supports PIPE interface. It has been adapted from xHCI v1.1 specification to be compact to meet embedded application needs. It is provided as Altera Qsys ready component and can be easily integrated in Qsys based system.

Block Diagram:

Features:

• Supports Super Speed (5 Gbps) mode
• Adapted from xHCI v1.1 Specification
  • Suitable solution for wide range of embedded applications
• Supports Control and Bulk transfers
• Integrated DMA Configurator
• Supports PIPE interface
• Supports Asynchronous Avalon clock interface
  • Enables you to run Avalon interface at clock frequency independent of USB 3.1 Gen 1 (USB 3.0) Link frequency
• Contains separate interface for Control Port and Data Port to improve Clock Domain Crossing (CDC) performance
• Supports Avalon 32-bit Interface for Integrating in Qsys
• Supports External PHY for USB 3.1 Gen 1 (USB 3.0) PIPE Interface
• Meets Altera Design Assistant guidelines

Future Enhancement:

• Low Speed(1.5 Mbps), Full Speed(12.0 Mbps) and High Speed(480 Mbps) support
• Interrupt and Isochronous transfers support
• ULPI interface support

Implementation Results:

Deliverables:

Applications:

• Set-up Box
• Printer
• Television
• Music system
• Mass storage
• Infotaintment

Support:

• IP integration support will be available with the purchase of full version
• IP Core modification support will be available at additional cost

Licensing:

• OpenCore Plus Evaluation : 1 month evaluation license at no cost
• Full : 1 Year development license with full version purchase for single project and single site
• Renewal : OpenCore Plus Evaluation license update at discounted price