Communications
Select from various SLS Communication soft cores to quickly complete your system design.
Description:
- Supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) modes
- Uses FPGA Transceiver as a PHY layer and thus eliminates need for external PHY for USB 3.2
- Provides well-known ULPI interface to interact with external USB 2.0 PHY
- Simple FIFO interface to transfer data over non-control endpoint
- Ready to use component
USB 3.0/3.1 Gen 1 Host Controller
The product is discontinued. For any queries, please contact, This email address is being protected from spambots. You need JavaScript enabled to view it. .
Description:
- Supports Low Speed (1.5 Mbps), Full Speed (12.0 Mbps), High Speed (480 Mbps) and SuperSpeed (5 Gbps)
- Supports External PHY or FPGA's built in 5+ Gbps Transceiver for USB 3.1 Gen 1 (USB 3.0) Interfac
- Follows xHCI v1.0 Specification and Supports Control, Bulk and Interrupt transfers
- Supports Avalon 32-bit Interface for Integrating in Qsys and Meets Altera Design Assistant guidelines
- Supports ULPI and PIPE interfaces
Description:
- Supports both full speed and high speed
- Pre-configured for 3 endpoints
- Support UTMI + Low Pin Interface (ULPI)
- Includes HAL Driver
Description:
- Supports both Full Speed (12 Mbps) and High Speed (480 Mbps)
- Support UTMI + Low Pin Interface (ULPI)
Description:
- Supports both Full Speed (12 Mbps) and High Speed (480 Mbps)
- Support UTMI + Low Pin Interface (ULPI)
Description:
- Supports both Full Speed and High Speed
- Support UTMI + Low Pin Interface (ULPI)
Description:
- Implementation of USB 1.1 specification for Altera devices
- Supports both full speed and low speed
- USB enumeration in hardware
- UTMI compliant physical layer interface
- CRC generation and checking
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