I²C (Inter-Integrated Circuit) Controller is a two-wire, bi-directional serial bus that provides simple and efficient method of data transmission over a short distance between many devices. Avalon compliant I²C Controller provides an interface between Nios II processor and I²C device. It can work as Master/Slave transmitter or Master/Slave receiver depending on working mode determined by Nios II processor. The I²C Controller IP core incorporates all features required by the latest I²C specification including clock synchronization, arbitration, multi-master systems and Fast-speed transmission mode.

It is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.

Block Diagram:

Features:

• Compatible with Philips I²C(PCF 8584) standard
• Supports both Master and Slave mode
• Automatic detection and adoption to bus interface type
• Multi-master operation
• Byte-by-byte data-transfer is driven by Interrupt or Bit-polling
• Arbitration-lost interrupt with automatic transfer cancellation
• Start/Stop/Repeated Start/Acknowledge generation
• Start/Stop/Repeated Start detection
• Bus-Busy detection
• Supports 7 bit addressing mode
• Operates from wide range of input clock frequencies
• Static synchronous design
• Avalon Bus compliant

Implementation Results:

Verification:

• The SLS I²C Controller IP Core's functionality is verified in ModelSim simulation software using test bench written in verilog HDL.
• The I²C Controller's functionality (as a Master) is tested by interfacing with RTC (Real Time Clock) and I²C EPROM on SLS UP3 Education Kit.
• The I²C Controller's functionality (as a Slave) is tested by communicating with another instance of the same core working as master and also with the SLS I²C Master IP Core on the UP3 Education Kit.

Deliverables:

Downloads:

• I²C Controller Documents