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I2C Controller

Model No. IPRI2CCMFP001

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I²C (Inter-Integrated Circuit) Controller is a two-wire, bi-directional serial bus that provides simple and efficient method of data transmission over a short distance between many devices. Avalon compliant I²C Controller provides an interface between Nios II processor and I²C device. It can work as Master/Slave transmitter or Master/Slave receiver depending on working mode determined by Nios II processor. The I²C Controller IP core incorporates all features required by the latest I²C specification including clock synchronization, arbitration, multi-master systems and Fast-speed transmission mode.

It is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.

Block Diagram:


  • Compatible with Philips I²C(PCF 8584) standard
  • Supports both Master and Slave mode
  • Automatic detection and adoption to bus interface type
  • Multi-master operation
  • Byte-by-byte data-transfer is driven by Interrupt or Bit-polling
  • Arbitration-lost interrupt with automatic transfer cancellation
  • Start/Stop/Repeated Start/Acknowledge generation
  • Start/Stop/Repeated Start detection
  • Bus-Busy detection
  • Supports 7 bit addressing mode
  • Operates from wide range of input clock frequencies
  • Static synchronous design
  • Avalon Bus compliant

Implementation Results:

Supported FamilyResource UtilizationPerformance ( Avalon Clock - fmax )
Cyclone III300 LE170MHz
Cyclone IV300 LE170MHz
Cyclone V300 LE170MHz
Stratix III210 LE200MHz
Stratix IV210 LE200MHz
Stratix V210 LE200MHz
Arria II155 LE235MHz
Arria V155 LE235MHz
MAX 10155 LE235MHz


  • The SLS I²C Controller IP Core's functionality is verified in ModelSim simulation software using test bench written in verilog HDL.
  • The I²C Controller's functionality (as a Master) is tested by interfacing with RTC (Real Time Clock) and I²C EPROM on SLS UP3 Education Kit.
  • The I²C Controller's functionality (as a Slave) is tested by communicating with another instance of the same core working as master and also with the SLS I²C Master IP Core on the UP3 Education Kit.


ContentsEvaluation LicenseFull Development License
License Type One (1) month evaluation license at no cost
Note: License can be extended for another month after examining request (Evaluation Now)
Encrypted IP Core Perpetual license for development
Note: Other licensing schemes and source code are also available
Reference Design Included for ESDK 1C6 Board Included for ESDK 1C6 Board
Nios II HAL Drivers Included in Object Code Included in Object Code
Note: Source Code available separately on request
Nios II Sample Applications
  • I2C Controller application using Interrupt
  • RTC application using Interrupt
  • I2C Controller application using Interrupt
  • RTC application using Interrupt
Simulation Library Altera Modelsim Altera Modelsim
Technical Documents
  • IP Core User Guide
  • Hardware and Simulation Tutorial
  • HAL API User Guide
  • IP Core User Guide
  • Hardware and Simulation Tutorial
  • HAL API User Guide
Technical Support Pre sales support from support team 1 Year integration support for Altera Quartus II





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System Level Solutions Inc. 511 N. Washington Avenue,Marshall, Texas 75670. Ph: 001-408-852-0067