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I2S Controller

Model No. IPR0I2SSFP001

Rating: Not Rated Yet



I²S Controller is designed to transfer audio data to and from Audio codec. It can be configured as both Master and Slave mode using software. The I²S IP is Phillips Inter IC Sound (I²S) specification compliant core for Altera devices.

It is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.

Block Diagram:


  • 8-bit and 16-bit sampling data width support
  • Variable sampling rate support
  • Used in both master/slave mode
  • Internal two 64 x 32 bit FIFO for data buffering
  • 32-bit DMA engine for both data transmit and receive for reducing CPU overhead
  • Transmit and Receive Operation
  • Compliant with the Avalon bus
  • Left and Right channel support

Implementation Results:

Supported FamilyResource UtilizationMemory BlocksPerformance ( Avalon Clock - fmax )
Cyclone III800 LE2 M9K176MHz
Cyclone IV815 LE2 M9K158MHz
Cyclone V339 ALM2 M10K141MHz
Stratix III512 ALUT2 M9K142MHz
Stratix IV514 ALUT2 M9K142MHz
Stratix V340 ALM2 M9K160MHz
Arria II514 ALUT2 M9K160MHz
Arria V318 ALM2 M10K192MHz
MAX 10769 LE2 M9K146MHz


  • I²S IP Core functionality is tested on NEEK kit.


ContentsEvaluation LicenseFull Development License
License Type One (1) month evaluation license at no cost
Note: License can be extended for another month after examining request (Evaluation Now)
Encrypted IP Core Perpetual license for development
Note: Other licensing schemes and source code are also available
Reference Design Included for NEEK Kit Included for NEEK Kit
Nios II Sample Applications I2S Application I2S Application
Simulation Library Altera Modelsim Altera Modelsim
Technical Documents
  • IP Core User Guide
  • Design from scratch tutorial
  • IP Core User Guide
  • Design from scratch tutorial
Technical Support Pre sales support from support team 1 Year integration support for Altera Quartus II






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