USB 1.1 Device, Software Based Enumeration (USB11SR)
Model No. IPRUSB1SFP002
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The USB 1.1 Device, Software Based Enumeration IP Core is RAM based USB 1.1 device core with 32-bit Avalon interface. The core supports Full Speed (12 Mbps) functionality and Low Speed (1.5 Mbps) functionality can be added as per customer request with additional charges. The core supports three preconfigured Control, Bulk IN and Bulk OUT endpoints. It can be configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis. Each configurable endpoints has an endpoint controller that supports Interrupt, Bulk and Isochronous transfers.
The core has been optimized for Intel (formerly Altera) FPGAs and its functionality has been verified on the hardware with Quartus II. The package includes ModelSim precompiled library for core simulation and verification.
Block Diagram:
Features:
- Verilog Implementation on RTL level
- Supports Full-speed (12 Mbps) transfer rate
- Software based USB enumeration Support
- Avalon Interconnection compliant
- Preconfigured for 3 endpoints
- CONTROL
- BULK IN
- BULK OUT
- Configurable for up to 15 IN/OUT endpoints which supports Bulk,Isochronous and Interrupt functionality on customer request at additional cost
- Cyclic redundancy code (CRC) checking/generation
- Data toggle synchronization mechanism
- Optimized for use with Altera NiosII embedded processor
Notes : (1) USB 1.1 Device IP Core with FIFO interface (USB11HF) is available on request at additional cost.Please contact support@slscorp.com
(2) The Low Speed functionality is available on customer request at additional charges.
FPGA Supported:
| FPGA | Supported Device Family |
| Intel |
Cyclone III, Cyclone IV, Cyclone V, Stratix III, Stratix IV, Stratix V, Arria II, Arria V, MAX10 |
Verification:
- USB11SR Device core's functionality is verified in ModelSim simulation software using test bench written in Verilog HDL
- USB11SR IP is also tested by interfacing with USB 1.1 PHY chip on SLS ESDK 1C12 Board
Deliverables:
| Contents | Evaluation License | Full Development License |
|---|---|---|
| License Type | One (1) month evaluation license at no cost Note: License can be extended for another month after examining request (Evaluation Now) |
Encrypted IP Core Perpetual license for development Note: Other licensing schemes and source code are also available |
| Reference Design | Included for ESDK 1C12 Board | Included for ESDK 1C12 Board |
| Demonstration | Mass Storage, Port Interface, Performance Test (Streaming Bulk IN and Bulk OUT), CDC Serial | Mass Storage, Port Interface, Performance Test (Streaming Bulk IN and Bulk OUT), CDC Serial |
| Nios II Sample Applications | Port Interface, Streaming | Port Interface, Streaming |
| Drivers |
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| Software Library (Compiled version) |
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| Utilities | USB View and Port Interface | USB View and Port Interface |
| Technical Documents |
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| Technical Support | Pre sales support from support team | 1 Year integration support for Altera Quartus II |
Support:
- IP integration support available with the purchase of full version
- Additional support on chargeable basis for a period of 3 months or more
- Core modification support available at additional cost
Licensing:
- OpenCore Plus Evaluation : 1 month evaluation license at no cost
- Full : 1 Year development license with full version purchase for single project and single site
- Renewal : OpenCore Plus Evaluation license update at discounted price
Downloads:
| << Back to USB 1.1 Device |
