Questions

Pre-sales

• What can I do with the evaluation version of your core? How does this compare to the full production version?

  The evaluation version of the eUSB 3.0 IP Core is the OpenCore plus evaluation of this megafunction and it operates in tethered mode. This means that the downloaded program will remain inside the hardware for a particular amount of time only i.e. for 2 hours. Once the program is downloaded and timeout occurs, the hardware evaluation IP Core will stop working. Also, the OpenCore plus hardware evaluation feature adds additional logic to the design that may affect the timing and fitting of the design. Therefore, you can check whether the core meets your design requirements with the evaluation version with this time limited feature and then confidently go for full production version for your final product. Initially, one (1) month evaluation license is provided which can be extended upon request and justification of the product evaluation needs.

• I want a hardware only solution for my product. I do not intend to use Nios II processor or SOPC builder. Do you have a solution?

  Yes, we do have a solution. Please contact This email address is being protected from spambots. You need JavaScript enabled to view it. for more details.

• Do you provide the source code for your IP?

  Yes, we can provide the source code of the IP at additional price on request.

• How many endpoints does the SLS eUSB 3.0 IP Core support?

  The eUSB 3.0 IP Core is pre-configured to support 3 endpoints - Control, Bulk In and Bulk Out. Additional endpoints are supported and can be added as per design requirements at additional cost.

• Can I customize the vendor ID in the full version?

  Yes, you can customize the vendor ID in full as well as evaluation version of the IP Core. You can customize the value in “sls_eusb.h” file provided in the IP Core setup.

• How do I request the evaluation version of the core?

  You can request evaluation version of IP Core from http://www.slscorp.com/licensing/ip-licensing.html page.

• What is the maximum speed achieved with the core?

  The maximum speed achieved with the IP Core is ~2Gbps for Bulk Out transfer and ~3Gbps for Bulk In transfer.

• In future, Is USB2.0 support possible with eUSB3.0 IP core ?

  No, there is no any possibility to add USB2.0 support with eUSB3.0 IP core.

• What features are not supported in eUSB3.0 compare to USB3.0 IP core?

  • List of features are not supported in eUSB3.0 IP core.
  • Power mode support
  • USB2.0 compatibility

• What are the main Advantages to use eUSB3.0 IP rather then USB3.0 IP core?

  eUSB3.0 IP core is a single chip solution, there is a no need for external Phy chip for physical layer functionality. This IP core reduced interface IOs to 4 and also not required any additional space on the board for External Phy chip.

IP Implementation

• How do I verify core functionality in hardware ?

  The SLS has developed a eUSB 3.0 board which provides all the accessibility to verify the eUSB 3.0 IP Core on hardware.

• I run the demo file as per the instructions mentioned in the readme file, but I am still getting 'USB device not recognized' message. How can I solve this problem? Is there some problem with the files I downloaded?

  There is nothing wrong with the demo you downloaded on the board. After successfully downloading the .elf file, run the usbview utility to verify the USB device connection. If the device is not connected properly, you will see the message “Enumeration failed” and in such case you will find the message USB device not recognized. To solve this error, follow the steps below:

  Plug in one end of the 'b' type USB cable to the device and other end to the PC. Check that the USB cable complies with the specification and it is not faulty. Connect the USB cable to another USB port.

• What is the use of 'EP0 buffer 0 read used word' and 'EP0 buffer1 write used word'?

  “EP0 buffer0 read used word” - indicates number of bytes present in buffer 0 register. “EP0 buffer1 write used word” - indicates number of bytes present in buffer 1 register.

• How can you make a request UNSTALL?

  There is no need to clear stalled control endpoint from software. It will clear automatically when next set up packet interrupt is generated.

• Can I read the register status for STALL in the EP0 disable register?

  EP0 disable register is a write only register and you cannot read the register status for STALL.

• Do we need to have some external FIFO’s to do just enumeration/receiving or sending small packages using EP0?

  No, need for external FIFO’s for enumeration, receiving or sending small packaging data.

• Is there any buffer/FIFO internally for EP0?

  Buffer memory is present for Endpoint 0 inside the core for IN and OUT data operation. Control Endpoint is handled by Nios II Controller.

Questions

Pre-sales

• Does SLS SD Host Controller IP have SDIO interface?

  No. The IP core does not support SDIO interface but we can give SDIO interface as design services. Please contact This email address is being protected from spambots. You need JavaScript enabled to view it. .

• What type of SD card does your IP core supports?

  The IP core supports SD as well as SDHC Memory cards.

• Does the core support DMA interface?

  Yes, the core supports DMA interface. You can take a look at the setup reference design for implementing DMA in the system design.

• Which mode does it supports for data communication?

  The core supports SD 1-bit and 4-bit mode for data communication as per SD Physical Layer Specification v2.0.

• What is the cost of the IP core?

  For the cost of the IP core please contact This email address is being protected from spambots. You need JavaScript enabled to view it. .

• What is the difference in OpenCore and Full version of IP core?

  In the evaluation version of the IP core, you will be able to generate the time-limited programming file for the hardware which will expire after pre-defined time period. Once the program is downloaded and timeout occurs, the hardware evaluation IP Core will stop working. Initially, one (1) month evaluation license is provided which can be extended upon request and justification of the product evaluation needs. In full version of the IP core, you will be able to generate the programming file without timing limit.

• What performance you have achieved using the IP Core?

  190 Mbits/Sec in read and 160 Mbits/Sec in write speed achieved with SD Host controller IP core. (With Sandisk 4 GB Extream II Card).

• Can I get the source code of HAL?

  You will get the source code of HAL after registered yourself on SD organization.

• Do you provide source code of the IP core?

  The standard version of IP Core does not come with the source code but can be provided on request and payment of a separate license fee. However, some software applications ship with full source and are listed in the deliverables.

• Does it comply with SD host Controller V2.0?

  The IP core follows SD physical layer specification v2.0 and it supports high SD high capacity card.

• How do I verify core functionality in hardware as well as in simulation?

  The IP Core package includes an embedded evaluation demonstration board that can be used to verify the core functionality in hardware. The package does not contain any simulation library, but in future releases it may include it.

• I want a hardware only solution for my product. I do not intend to use Nios II processor or SOPC builder. Do you have a solution?

  No. it is not possible to use only core. You must have to use the SD host controller with the Nios II processor. But it may change as per the processor used in the design.

• Does the core support FPGA other than Altera?

  The package only supports Altera FPGA. If customer wants to implement it FPGA other than Altera then we can work mutually on design service agreement. For this please contact This email address is being protected from spambots. You need JavaScript enabled to view it. .

IP Implementation

• Are DSP builder blocks provided for reading and writing to the SD card?

  No, there is no DSP builder blocks provided, but we provide a ready to use reference design for using SD Card using our SD Host Controller IP Core (the core is required to be downloaded separately from the website).

• Does the IO bank on the cyclone that interfaces with the SD Card have to run on 3.3V?

  Any IO which operates on 3.3 voltage level can be used for SD Card interface.

• How does the IP Core decide the SD clock frequency? What is the maximum frequency supported?

  The Ip Core supports variable clock frequencies that can be selected using the software.You can set SD Clock frequency by writing the value in to the Control register or using the sdhc_set_frequency() API. In C file, "sd_info.sdhc_clock" is used to define SD Host IP core clock given in SOPC. On the basis of this, the SD host controller decides the pre-scale value to calculate the frequency for the SD card. As per the specification SD Host should support a maximum of 50 MHz for High Speed card and a maximum of 25 MHz for normal card. Now if your card supports the High Speed mode then it will be automatically detected and the frequency will be set accordingly. Hence, for High Speed card, the clock won't increase more than 50 MHz and for normal card it won't increase more than 25 MHz.

• How much block length does the IP core support?

  IP core supports variable block length to read/write to/from SD card. The block length is programmed by writing to BlockLength register in the software.

• I am getting 'ERROR: Failed to send CMD(5) due to command time out condition' error message. What does it mean?

  CMD[5] is used for the identification of the inserted SDIO card. The message will be displayed only when the card inserted is not a SDIO card.

• I am getting 'Unable to mount FAT File System on SD Card' error message. What does it mean?

  There are mainly two reasons for getting this error message:

  • The data read/write memory is not connected with the SDHC IP component in the SOPC Builder or Qsys.
  • The SD card is not formatted with the FAT file system

• Is it allowed to format the SD Card on a windows PC?

  Yes, it is allowed to format the SD Card on a windows PC. Please select "512 Bytes" under "Allocation unit size" in the Format window.

• Does the IP Core supports to get an interrupt when the DMA completes the write operation?

  Yes, the current IP Core setup has the feature to provide an interrupt when the DMA completes the write operation. For implementation, please contact This email address is being protected from spambots. You need JavaScript enabled to view it. .

• Do you provide any documentation of the rockbox FAT file system?

  The rockbox is an open source file system. The detailed documentation is available at rockbox community.

Related Link

• Licensing/Installation

Questions

• Which type of documents do you provide in USB 3.2 Gen 2 IP Core Setup?

  We are providing user guides of the IP Core and HAL API. Along with each reference design, we are providing quick start document. Using it, user can easily extract and recompile the provided reference design at his/her end. Also, we are providing a document that helps user to create software project.

• Which type of Host Controllers have been used to verify your USB 3.2 Gen 2 IP Core?

  USB 3.2 Gen 2 IP Core has been verified using ASMedia and Intel Gen 2 Host Controllers.

• How much speed is achieved during raw read write data streaming?

  We have achieved around 8.5 Gbps speed during IN transfer and 8.7 Gbps during OUT transfer. 

• How should we request evaluation package of your USB 3.2 Gen 2 IP Core?

  For evaluation, please visit at https://www.slscorp.com/licensing/ip-licensing.html.

• Which communication modes are supported by USB 3.2 Gen 2 IP core?

  USB 3.2 Gen 2 IP core supports Gen 2 (Super Speed Plus), Gen 1 (Super Speed) as well as backward compatible with USB 2.0 mode. User can also use this IP core in USB 2.0 mode only.

• Does USB 3.2 Gen 2 IP Core use FPGA's inbuilt transceiver for all modes (Super Speed Plus, Super Speed and USB 2.0)?

  USB 3.2 Gen 2 IP Core uses FPGA's inbuilt transceiver for Gen 2 (Super Speed Plus) and Gen 1 (Super Speed) modes only. To use IP Core in USB 2.0 mode (High/Full/Low Speed), external PHY chip is needed.

• Does USB 3.2 Gen 2 IP Core require external PHY chip?

  To use USB 3.2 Gen 2 IP Core in USB 2.0 mode, you will require external PHY. Following are the reasons why we need an external PHY chip for USB2.0. (1) USB requires both differential and single ended signalling. Certain bus states are indicated by single ended signals. For example, single ended zero (SE0) is used to perform USB reset operation. It is generated by holding both D+ and D- lines at low. During data transfer, it uses differential signaling.

  In order to get more idea, you are requested to refer section 7.1 Signalling from USB2.0 Specification. (2) It also uses some pull-up or pull-down registers. Either some pull-up registers or termination registers need to be attached or detached during run-time. For example, after speed negotiation, high speed device needs to enable high speed terminations on both D+/D- lines and needs to remove pull-up resistor from D+ lines.

• Which external PHY chips does your USB 3.2 Gen 2 IP Core support?

  USB 3.2 Gen 2 IP Core (in USB 2.0 mode) supports any ULPI compliant PHY chips. It has been verified on Microchip's USB3320, USB3340, USB3300, Richnex's RN1133.

• Which items are you providing in your USB 3.2 Gen 2 IP Core setup?

  • User Guide of IP Core and HAL API
  • Encrypted IP Core
  • Reference Designs
  • Ready to use Demonstrations

• Are you providing any reference design for evaluating your USB 3.2 Gen 2 IP Core?

  Yes, we provide reference design for respective Development Board and eUSB 3.1 FMC Snap On Board.

• Which FPGA device falmilies do your USB 3.2 Gen 2 IP Core support?

  FPGA	Supported Device Family
  Intel	Gen 2 mode with backward compatibility: Agilex 7, Stratix10, Arria10, Cyclone10  Gen 1 mode with backward compatibility: Cyclone V, Arria V, Stratix V
  Microchip	Gen 2 mode with backward compatibility: Polarfire, PolarFire SoC
  Lattice Semiconductor	Gen1 mode with backward compatibility: CrossLink-NX

• Are you providing reference design for FPGA development tool?

  Yes. Please write us at This email address is being protected from spambots. You need JavaScript enabled to view it.

• Does SLS USB 3.2 Gen 2 IP Core USB-IF Certified?

  Please write us at This email address is being protected from spambots. You need JavaScript enabled to view it.

• How many transfer types does your USB 3.2 Gen 2 IP Core support?

  IP Core supports Control, Bulk, Interrupt and Iscochronous transfer types.

• Low Power mode support.

  We are not supporting the Low Power modes for Gen 2 and Gen 1.

• Which interface does USB 3.2 Gen 2 IP Core support?

  USB 3.2 Gen 2 IP Core supports Avalon, AXI4 and AHB-L interface.

• Do you have any ready to use demonstration?

  Yes. We have ready to use demonstration of streaming application as well as Loopback test. USB 3.2 Gen 2 IP Core demonstration for Mass Storage and UVC will be provided based on request.

• Don’t want to use soft processor. Explain use of soft processor in IP core.

  Use of soft processor (e.g. NIOS, Mi-V, RISC V MC) is to manage the communication for control EP (EP0) only. For non-zero endpoint, you need to write your own RTL logic. Footprint of code is small and can fit into FPGA onchip RAM. We do provide ready to use HAL source with IP core to minimize user's efforts.

• Does the IP support LFPS?

  Yes. IP Supports LFPS. Although Intel FPGA transceiver does not support RX Electrical idle, IP core uses glue logic to detect LFPS.

• Does this IP core for USB 3.2 (20Gbps)?

  As of now it support USB 3.2 Gen2x1 (10Gbps). Currently we are working to develop USB 3.2 Gen 2x2 Device IP Core.

Questions

Pre-sales

• What can I do with the evaluation version of your core? How does this compare to the full production version?

  The evaluation version of the USB 3.0 IP Core is the OpenCore plus evaluation of this megafunction and it operates in tethered mode. This means that the downloaded program will remain inside the hardware for a particular amount of time only i.e. for 2 hours. Once the program is downloaded and timeout occurs, the hardware evaluation IP Core will stop working. Also, the OpenCore plus hardware evaluation feature adds additional logic to the design that may affect the timing and fitting of the design. Therefore, you can check whether the core meets your design requirements with the evaluation version with this time limited feature and then confidently go for full production version for your final product. Initially, one (1) month evaluation license is provided which can be extended upon request and justification of the product evaluation needs.

• I want a hardware only solution for my product. I do not intend to use Nios II processor or SOPC builder. Do you have a solution?

  Yes, we do have a solution. Please contact This email address is being protected from spambots. You need JavaScript enabled to view it. for more details.

• Do you provide the source code for your IP?

  Yes, we can provide the source code of the IP at additional price on request.

• How many endpoints does the SLS USB 3.0 IP Core support?

  The USB 3.0 IP Core is preconfigured to support 3 endpoints - Control, Bulk In and Bulk Out. Additional endpoints are supported and can be added as per design requirements at additional cost.

• Can I customize the vendor ID in the full version?

  Yes, you can customize the vendor ID in full as well as evaluation version of the IP Core. You can customize the value in "sls_usb.h" file provided in the IP Core setup.

• How do I request the evaluation version of the core?

  You can request the evaluation version of the IP Core from http://www.slscorp.com/ip-cores/communication/usb-30-device.html page. Click on the request eval button on the top of the page. It asks you to sign in or register to send the request of IP Core and its evaluation license file.

• How do I verify core functionality in hardware as well as in simulation?

  The IP Core package includes the USB 3.0 Development board (http://www.slscorp.com/products/development-boards/usb-3-0-development-board.html) that can be used to verify the functionality in hardware. The package also includes the ModelSim precompiled library to simulate the design and verify the basic transaction.

• What is the maximum speed achieved with the core?

  The maximum speed achieved with the IP Core is ~1.5Gbps for Bulk Out transfer and ~2Gbps for Bulk In transfer.

IP Implementation

• How do I verify core functionality in hardware as well as in simulation?

  The SLS has developed a USB 3.0 board which provides all the accessibility to verify the USB 3.0 IP Core on hardware. The IP Core package includes a ModelSim precompiled library to simulate the design and verify basic transactions.

• I run the demo file as per the instructions mentioned in the readme file, but I am still getting 'USB device not recognized' message. How can I solve this problem? Is there some problem with the files I downloaded?

  There is nothing wrong with the demo you downloaded on the board. After successfully downloading the .elf file, run the usbview utility to verify the USB device connection. If the device is not connected properly, you will see the message "Enumeration failed" and in such case you will find the message USB device not recognized. To solve this error, follow the steps below:

  • Plug in one end of the 'b' type USB cable to the device and other end to the PC.
  • Check that the USB cable complies with the specification and it is not faulty.
  • Connect the USB cable to another USB port.

• How can I configure the core to support a crystal input or external clock mode?

  Our IP core supports both crystal input and external clock input. For clock input, the IP Core has provided the reset_cnt.v file in which you have to set the xtal_remove and phy_xtal_sel_bit based on the clock input. The reference design for USB 3.0 development board uses the external clock input generated from IP Core. Based on the bit selection the clock is generated from the SDRAM_PLL and feed to the TI PHY chip.

• Does u30_rx_elecIDLE bidirectional pin effect the input clock?

  No, u30_rx_elecIDLE bidirectional pin doesn't affect the clock input to TI-PHY.

• What is the use of 'EP0 buffer 0 read used word' and 'EP0 buffer1 write used word'?

  'EP0 buffer0 read used word' - indicates number of bytes present in buffer 0 register. 'EP0 buffer1 write used word' - indicates number of bytes present in buffer 1 register.

• How can you make a request UNSTALL?

  There is no need to clear stalled control endpoint from software. It will clear automatically when next set up packet interrupt is generated.

• Can I read the register status for STALL in the EP0 disable register?

  EP0 disable register is a write only register and you cannot read the register status for STALL.

• Can USB 3.0 development board operate at 500 MB/sec?

  As per the USB 3.0 IP Core specification, the maximum data transfer speed is 4.8 Gbps (500 MB/sec). But in actual the delay and overhead by the PHY, Link and Proto layers reduces the speed for data communication by ~1.5 Gbps. Also while communicating with the device we have to consider the overhead of the host controller as well. Hence it also reduces the speed at ~1.8 to 2 Gbps. By taking in account all these factors, we are able to achieve ~1.5 Gbps write and 2.5 Gbps read speed.

• Do we need to have some external FIFO's to do just enumeration/receiving or sending small packages using EP0?

  No, need for external FIFO's for enumeration, receiving or sending small packaging data.

• Is there any buffer/FIFO internally for EP0?

  Buffer memory is present for Endpoint 0 inside the core for IN and OUT data operation. Control Endpoint is handled by Nios II Controller.

• What is the function of LINK_ERROR_REG?

  In this register due to the direct value of the current state assignment it generates a continuous interrupt to the software. Please refer USB 3.0 IP Core user guide for more information.

Related Link

• Licensing/Installation