Questions

Pre-sales

• What is the difference between the evaluation OpenCores USB 2.0 Device IP Core and the full license SLS USB 2.0 Device IP Core?

  The SLS USB 2.0 Device IP Core contains several additional features listed below that are not provided in the OpenCores USB 2.0 IP package:

  • SLS USB 2.0 Device IP Core is delivered with HAL API for software support
  • The IP package includes Windows drivers
  • Support contract: SLS IP Core is fully supported by a team of design engineers
  • The SLS USB 2.0 Device IP Core contains hooks for passing USB compliance testing

• Do you have a USB 2.0 Host Core?

  Yes, we do have an Embedded USB 2.0 Host Controller IP core that supports memory sticks. The evaluation version of the core can be downloaded from http://www.slscorp.com/ip-cores/communication/usb-20-host.html.

• What can I do with the evaluation version of your core? How does this compare to the full production version?

  The evaluation version of the USB 2.0 IP Core is the OpenCore plus evaluation of this megafunction and it operates in tethered mode. This means that the downloaded program will remain inside the hardware for a particular amount of time only. Once the program is downloaded and timeout occurs, the hardware evaluation IP Core will stop working. Also, the OpenCore plus hardware evaluation feature adds additional logic to the design that may affect the timing and fitting of the design. Therefore, you can check whether the core meets your design requirements with the evaluation version with this time limited feature and then confidently go for full production version for your final product. Initially, one (1) month evaluation license is provided which can be extended upon request and justification of the product evaluation needs.

• I want a hardware only solution for my product. I do not intend to use processor. Do you have a solution?

  Yes, we do have a solution. A variant of USB 2.0 Device Controller core - USB20HF has a FIFO interface. This means, it communicates with external world using FIFOs instead of Avalon/AXI/AHB Lite interface. This version occupies minimum of FPGA resources and it can be used for simpler and hardware based USB 2.0 solutions. The evaluation version of the core can be downloaded from http://www.slscorp.com/ip-cores/communication/usb-20-device/usb20hf.html.

• Do you provide the source code for your IP?

  The standard version of the SLS USB 2.0 IP Core does not come with the source code but can be provided on request and payment of a separate license fee. However, some software applications ship with full source and are listed in the deliverables.

• How many endpoints does the SLS USB 2.0 IP Core support?

  The standard IP version is preconfigured for three (3) endpoints (Control, Bulk In and Bulk Out). Up to a total of fifteen (15) endpoints are supported and may be added as per design requirements at additional cost.

• Can I get the open source code for HAL?

  The open source code of HAL is available on request at additional price. Please contact This email address is being protected from spambots. You need JavaScript enabled to view it.

• Can I customize the vendor ID in the full version?

  Yes, we provide the utility to customize product ID and vendor ID in the full version SLS USB 2.0 IP core.

• How do I verify core functionality in hardware as well as in simulation?

  The SLS USB 2.0 IP Core package includes reference design for vendor specific development board to verify the core functionality in hardware. The package also includes a Simulation library to simulate the design and verify basic transactions.

• We plan to use uC/USB (A Micrium product) with the SLS USB 2.0 IP core. Can you please confirm compatibility?

  The SLS USB 2.0 IP Core, as with Processor, is compatible with the Micrium uC RTOS. One can modify the source or drivers to support different operating systems as a design service. Please contact at This email address is being protected from spambots. You need JavaScript enabled to view it. to request a quote. Note that we require customers to provide us with access to their OS of choice so that we may do the porting and driver development.

IP Implementation

• How do I verify core functionality in hardware as well as in simulation?

  The SLS USB 2.0 IP Core package includes the reference design for vendor specific development board to verify the core functionality in hardware. The package also includes a Simulation library to simulate the design and verify basic transactions.

• I start the test application as per the instructions in the manual, but I still get a 'USB device not recognized.' Message. How can I solve this problem? Is there some problem with the files I downloaded?

  There is nothing wrong with the application or the files downloaded. After successfully downloading the .elf file, run the usbview utility to verify the USB device connection. If the device is not connected properly, you will see the message "Enumeration failed" and in such case you will find the the message USB device not recognized. To solve this error, follow the steps below:

  • Plug in one end of the 'b' type USB cable to the device and other end to the PC.
  • Check that the USB cable comply with the specification and it is not faulty.
  • Connect the USB cable to another USB port.

• When performing Bulk operation, how do I determine how many bytes were received?

  The HAL driver API on the Processor side returns the count value of the number of bytes received.

• Is there a method to know if the device is successfully enumerated? If not, can I force enumeration?

  Yes, the speed negotiation register may be read and the appropriate bit extracted. Yes enumeration may be forced using the disconnect API. This will force the PHY chip to disconnect, and reconnection will occur using the connect API.

• Does the Data Cache create a problem?

  Data cache can not create any hardware related problem. It can give mismatch of data value if cache is not handled properly on software side.

• Can you provide USB HOST Stack? Is it necessary to run one OS for the USB?

  We do provide USB Host Stack, but not in source code form. Also, no OS is required since our stack is a standalone stack.

• In USB20SR, is it necessary to set _DMA_USE macro to 1 in the application to use DMA functionality?

  _DMA_USE macro is used to set the DMA functionality in the system for data transfer. If you want to use DMA for data transfer then set _DMA_USE macro to 1 else set to 0. When it is set to 1, make sure that dma_config() function will be called before calling the USB data transfer function using DMA e.g. usb20sr_with_dma_xxx(). dma_config() function should be called with respective DMA information which is connected with USB IP core for data transfer. If the macro is set to 0 and any USB data transfer function using DMA is called then it will result in an error.

• When is the correct time to call dma_config () function while using USB20SR IP core?

  It is preferable to call dma_config() function before doing first bulk data transfer operation. return to top

• What is the difference between with DMA functions and without DMA functions in USB20SR?

  There is no difference in the functions except use of DMA for data transfer. If you are using with DMA functions then it will use the DMA for data transfer and without DMA functions will not use DMA. If you are using with DMA functions then you must need to configure the USB20SR driver for DMA transfer by calling dma_config() function before calling with DMA functions. For without DMA functions, you do not need to use dma_config() function.

• Why the device sometimes fails to enumerate on the Front USB Port of the PC?

  The Front USB Port is a dongle which is connected to the hardware using cables. Hence there is possibility of mismatching the length of D+ and D- lines of USB and that sometimes causes USB to fail enumerating the device.

• We do not have power control mechanism in our USB board design. Can you give us any advice that we can use to reduce FPGA current draw prior to the completion of USB enumeration?

  In case there is no scope of power control on the board, following can be done in the FPGA design for reducing the FPGA current draw prior to the completion of USB enumeration: Just keep the USB and Processor block running and try to turn off/disable or reset the AFE controller block and other blocks in the FPGA design. Once enumeration gets completed, enable the rest of the blocks.

Related Link

• Licensing/Installation