Questions

• Which type of documents do you provide in USB 3.2 Gen 2 IP Core Setup?

  We are providing user guides of the IP Core and HAL API. Along with each reference design, we are providing quick start document. Using it, user can easily extract and recompile the provided reference design at his/her end. Also, we are providing a document that helps user to create software project.

• Which type of Host Controllers have been used to verify your USB 3.2 Gen 2 IP Core?

  USB 3.2 Gen 2 IP Core has been verified using ASMedia and Intel Gen 2 Host Controllers.

• How much speed is achieved during raw read write data streaming?

  We have achieved around 8.5 Gbps speed during IN transfer and 8.7 Gbps during OUT transfer. 

• How should we request evaluation package of your USB 3.2 Gen 2 IP Core?

  For evaluation, please visit at https://www.slscorp.com/licensing/ip-licensing.html.

• Which communication modes are supported by USB 3.2 Gen 2 IP core?

  USB 3.2 Gen 2 IP core supports Gen 2 (Super Speed Plus), Gen 1 (Super Speed) as well as backward compatible with USB 2.0 mode. User can also use this IP core in USB 2.0 mode only.

• Does USB 3.2 Gen 2 IP Core use FPGA's inbuilt transceiver for all modes (Super Speed Plus, Super Speed and USB 2.0)?

  USB 3.2 Gen 2 IP Core uses FPGA's inbuilt transceiver for Gen 2 (Super Speed Plus) and Gen 1 (Super Speed) modes only. To use IP Core in USB 2.0 mode (High/Full/Low Speed), external PHY chip is needed.

• Does USB 3.2 Gen 2 IP Core require external PHY chip?

  To use USB 3.2 Gen 2 IP Core in USB 2.0 mode, you will require external PHY. Following are the reasons why we need an external PHY chip for USB2.0. (1) USB requires both differential and single ended signalling. Certain bus states are indicated by single ended signals. For example, single ended zero (SE0) is used to perform USB reset operation. It is generated by holding both D+ and D- lines at low. During data transfer, it uses differential signaling.

  In order to get more idea, you are requested to refer section 7.1 Signalling from USB2.0 Specification. (2) It also uses some pull-up or pull-down registers. Either some pull-up registers or termination registers need to be attached or detached during run-time. For example, after speed negotiation, high speed device needs to enable high speed terminations on both D+/D- lines and needs to remove pull-up resistor from D+ lines.

• Which external PHY chips does your USB 3.2 Gen 2 IP Core support?

  USB 3.2 Gen 2 IP Core (in USB 2.0 mode) supports any ULPI compliant PHY chips. It has been verified on Microchip's USB3320, USB3340, USB3300, Richnex's RN1133.

• Which items are you providing in your USB 3.2 Gen 2 IP Core setup?

  • User Guide of IP Core and HAL API
  • Encrypted IP Core
  • Reference Designs
  • Ready to use Demonstrations

• Are you providing any reference design for evaluating your USB 3.2 Gen 2 IP Core?

  Yes, we provide reference design for respective Development Board and eUSB 3.1 FMC Snap On Board.

• Which FPGA device falmilies do your USB 3.2 Gen 2 IP Core support?

  FPGA	Supported Device Family
  Intel	Gen 2 mode with backward compatibility: Agilex 7, Stratix10, Arria10, Cyclone10  Gen 1 mode with backward compatibility: Cyclone V, Arria V, Stratix V
  Microchip	Gen 2 mode with backward compatibility: Polarfire, PolarFire SoC
  Lattice Semiconductor	Gen1 mode with backward compatibility: CrossLink-NX

• Are you providing reference design for FPGA development tool?

  Yes. Please write us at This email address is being protected from spambots. You need JavaScript enabled to view it.

• Does SLS USB 3.2 Gen 2 IP Core USB-IF Certified?

  Please write us at This email address is being protected from spambots. You need JavaScript enabled to view it.

• How many transfer types does your USB 3.2 Gen 2 IP Core support?

  IP Core supports Control, Bulk, Interrupt and Iscochronous transfer types.

• Low Power mode support.

  We are not supporting the Low Power modes for Gen 2 and Gen 1.

• Which interface does USB 3.2 Gen 2 IP Core support?

  USB 3.2 Gen 2 IP Core supports Avalon, AXI4 and AHB-L interface.

• Do you have any ready to use demonstration?

  Yes. We have ready to use demonstration of streaming application as well as Loopback test. USB 3.2 Gen 2 IP Core demonstration for Mass Storage and UVC will be provided based on request.

• Don’t want to use soft processor. Explain use of soft processor in IP core.

  Use of soft processor (e.g. NIOS, Mi-V, RISC V MC) is to manage the communication for control EP (EP0) only. For non-zero endpoint, you need to write your own RTL logic. Footprint of code is small and can fit into FPGA onchip RAM. We do provide ready to use HAL source with IP core to minimize user's efforts.

• Does the IP support LFPS?

  Yes. IP Supports LFPS. Although Intel FPGA transceiver does not support RX Electrical idle, IP core uses glue logic to detect LFPS.

• Does this IP core for USB 3.2 (20Gbps)?

  As of now it support USB 3.2 Gen2x1 (10Gbps). Currently we are working to develop USB 3.2 Gen 2x2 Device IP Core.