USB 3.0/3.1 Gen 1 Device, Software based enumeration FIFO Interface (USB30SF)
Model No. IPRUSB3SFP001
This IP Core is now upgraded to eUSB 3.1 Gen 2 Device Controller (eUSB31SF) with backward compatibility, using FPGA in-built 10/5 Gbps transceiver. We recommend to use new version for new design. For detail, please visit eUSB 3.1 Gen 2 Device Controller (eUSB31SF)
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The SLS USB 3.0/3.1 Gen 1 IP Core is the SuperSpeed core that supports connectivity between TI USB 3.0/3.1 Gen 1 PHY (TUSB1310 ) and Altera® FPGA. The IP Core is wrapped around with software drivers and examples for its ease of use and quick integration. The ready to use USB 3.0 development board availability makes the integration faster. The IP Core package also contains the reference design that can be used directly for starting a custom application development.
The IP Core has been optimized for Altera® FPGAs and its functionality has been verified on the hardware with Altera® Quartus II software. The package includes ModelSim precompiled library for IP Core simulation and verification.
Development Board:
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Actual Performance Data:
Although the SLS USB 3.0/3.1 Gen 1 IP Core is designed and proven working at maximum throughput in a point to point environment, in reality the overall systsem determines the real speed implementation would experience.
Notice: All Host Controllers are not cerated equally!!!
Block Diagram:
Features:
- Implementation of Link Layer & Protocol Layer
- Support 16-bit and 32-bit Phy layer data interface
- Supports CONTROL, BULK transfer without stream support
- USB2.0 backward compatible
- All Link layer power state handling
- Implements CRC calculation and generation in hardware
- Configurable end-point selection
Implementation Results:
| Supported Family | Resource Utilization | Memory Blocks | Performance ( Avalon Clock - fmax ) |
|---|---|---|---|
| Cyclone IV | 10000 LE | 36 M9K | 250MHz |
| Cyclone V | 4710 ALM | 35 M10K | 405MHz |
| Stratix III | 5340 ALUT | 33 M9K | 730MHz |
| Stratix IV | 5215 ALUT | 33 M9k | 412MHz |
| Stratix V | 4797 ALM | 10 M20K | 717.36MHz |
| Arria II | 5497 ALM | 30 M9K | 700.28MHz |
| Arria V | 4703 ALM | 35 M10K | 338.41MHz |
| MAX 10 | 10000 LE | 36 M9K | 250MHz |
Verification:
- USB 3.0/3.1 Gen 1 IP core's functionality is verified in ModelSim simulation software using test bench written in Verilog HDL.
Deliverables:
| Contents | Evaluation License | Full Development License |
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| License Type | One (1) month evaluation license at no cost Note: License can be extended for another month after examining request (Evaluation Now) |
Encrypted IP Core Perpetual license for development Note: Other licensing schemes and source code are also available |
| Reference Design | Included for SLS USB3.0 board | Included for SLS USB3.0 board |
| SLS USB3.0 Board | Not included, need to purchase separately | Included |
| Demonstration |
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| Nios II Sample Applications (with C code) | Enumeration | Enumeration |
| Drivers | Windows Reference Drivers (object code) | Windows Reference Drivers (object code) |
| Software Library (Compiled version) |
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| Simulation Library | Altera ModelSim | Altera ModelSim |
| Utilities | USB View, Amcap and Enumeration Data Editor | USB View, Amcap and Enumeration Data Editor |
| Technical Documents |
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| Technical Support | Pre sales support from support team | 1 Year integration support for Altera Quartus II |
Downloads:
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