eUSB 3.0/3.1 Gen 1 Device Controller (eUSB30SF)
Model No. IPRUSB3SFP002
This IP Core is now upgraded to eUSB 3.1 Gen 2 Device Controller (eUSB31SF) with backward compatibility, using FPGA in-built 10/5 Gbps transceiver. We recommend to use new version for new design. For details, please visit eUSB 3.1 Gen 2 Device Controller (eUSB31SF)
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USB 3.0/3.1 Gen 1 standard is ubiquitous across the world and has raised the demand to implement it in various products. The integration of USB 3.0/3.1 Gen 1 Device with FPGA development board needs 60+ I/O for USB 3.0/3.1 Gen 1 PHY chip to connect it with FPGA. This adds an extra cost to the board. Altera has introduce the FPGA which has in built transceiver which run at 5Gbps speed (same as USB 3.1 Gen 1 (USB 3.0) Specification) with features like 8b/10b, SKIP control etc. required during implementing USB 3.0/3.1 Gen 1 Controller. SLS has integrate the USB 3.1 Gen 1 Device IP Core with the Altera Transceiver and USB 2.0 PHY chip, and developed the eUSB 3.1 Gen 1 Device Controller IP Core, offering low cost solution.
The eUSB 3.1 Gen 1 Device Controller IP Core is SuperSpeed Core developed by SLS to provide better solutions and options to user for implementation of USB 3.0/3.1 Gen 1 interface in their design. There is no need for external USB 3.1 Gen 1 PHY chip because IP Core supports SuperSpeed operation with Altera Transceiver running at 5Gbps in FPGA and High Speed operation with external USB 2.0 Transceiver PHY chip. This will reduces the I/O pin for USB 3.1 Gen 1 connection from 60+ to 18 and also saves board space. This provides a compatible link to both USB 3.1 Gen 1 and USB 2.0 Device for an embedded applications. The SLS eUSB 3.0 HSMC Snap On Board provides a platform for verification and testing of the IP Core.
eUSB 3.0 HSMC Snap On Board:
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Block Diagram:
Features:
- Supports SuperSpeed operation with Altera Transceiver running at 5Gbps in FPGA and High Speed operation with External USB 2.0 Transceiver PHY chip
- Implementation of PHY Layer (with Altera 5Gbps Transceiver), Link Layer and Protocol Layer
- Supports 8b/10b, SKIP Control
- Supports configurable Endpoint selection
- Avalon bus compliant
- Complete software based control for device enumeration and control request
Implementation Results:
| Supported Family | Resource Utilization | Memory Blocks |
|---|---|---|
| Cyclone V GT/ST SoC | 6000 ALM | 39 M10K |
| Stratix V GX/GS/GT | 6200 ALM | 26 M20K |
| Arria V GX/GT/GZ/SX SoC/ST SoC | 5800 ALM | 42 M10K |
Deliverables:
| Contents | Evaluation License | Full Development License |
|---|---|---|
| License Type | One (1) month evaluation license at no cost Note: License can be extended for another month after examining request (Evaluation Now) |
Encrypted IP Core Perpetual license for development Note: Other licensing schemes and source code are also available |
| Reference Design | Included for Altera Cyclone V GT Development Board | Included for Altera Cyclone V GT Development Board |
| SLS eUSB3.0 Board | Not included, need to purchase separately | Included |
| Demonstration |
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| Nios II Sample Applications (with C code) | Enumeration | Enumeration |
| Drivers | Windows Reference Drivers (object code) | Windows Reference Drivers (object code) |
| Software Library (Compiled version) |
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| Simulation Library | Altera Modelsim | Altera Modelsim |
| Utilities | USB View | USB View |
| Technical Documents |
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| Technical Support | Pre sales support from support team | 1 Year integration support for Altera Quartus II |
Application:
- USB 3.0/3.1 Gen 1 Device based applications
- USB 2.0 Device/Host/OTG based applications
Support:
- IP integration support available with the purchase of full version
- Additional support on chargeable basis for 3 months or more Core modification support available at additional cost
Licensing:
- OpenCore Plus Evaluation : 1 month evaluation license at no cost
- Full : 1 Year development license with full version purchase for single project and single site
Downloads:
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